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文章速递Metasurface-based subtractive color filter fabricated on a 12-inch glass wafer using a CMOS platform 认领
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作者 ZHENGJI XU NANXI LI +7 位作者 YUAN DONG YUAN HSING FU TING HU QIZE ZHONG YANYAN ZHOU DONGDONG Li SHIYANG ZHU NAVAB SINGH 《光子学研究:英文版》 SCIE EI CAS CSCD 2021年第1期13-20,共8页
Optical color filters are widely applied in many areas including display,imaging,sensing,holography,energy harvest,and measurement.Traditional dye-based color filters have drawbacks such as environmental hazards and i... Optical color filters are widely applied in many areas including display,imaging,sensing,holography,energy harvest,and measurement.Traditional dye-based color filters have drawbacks such as environmental hazards and instability under high temperature and ultraviolet radiation.With advances in nanotechnology,structural color filters,which are based on the interaction of light with designed nanostructures,are able to overcome the drawbacks.Also,it is possible to fabricate structural color filters using standard complementary metal-oxide-semiconductor(CMOS)fabrication facilities with low cost and high volume.In this work,metasurface-based subtractive color filters(SCFs)are demonstrated on 12-inch(300-mm)glass wafers using a CMOS-compatible fabrication process.In order to make the transmissive-type SCF on a transparent glass wafer,an in-house developed layer transfer process is used to solve the glass wafer handling issue in fabrication tools.Three different heights of embedded silicon nanopillars(110,170,and 230 nm)are found to support magnetic dipole resonances.With pillar height and pitch variation,SCFs with different displayed colors are achieved.Based on the resonance wavelength,the displayed color of the metasurface is verified within the red-yellow-blue color wheel.The simulation and measurement results are compared and discussed.The work provides an alternative design for high efficiency color filters on a CMOS-compatible platform,and paves the way towards mass-producible large-area metasurfaces. 展开更多
关键词 glass wafer overcome
文章速递A comparative study of rhenium coatings prepared on graphite wafers by chemical vapor deposition and electrodeposition in molten salts 认领
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作者 Jiang-Fan Wang Shu-Xin Bai +2 位作者 Yi-Cong Ye Li-An Zhu Hong Zhang 《稀有金属:英文版》 SCIE EI CAS CSCD 2021年第1期202-211,共10页
The purity,preferred orientation,microstructure,microhardness,bonding strength,thickness uniformity and thermal stability of rhenium(Re)coatings prepared on graphite wafers by chemical vapor deposition(CVD)and electro... The purity,preferred orientation,microstructure,microhardness,bonding strength,thickness uniformity and thermal stability of rhenium(Re)coatings prepared on graphite wafers by chemical vapor deposition(CVD)and electrodeposition(ED)in molten salts were comparatively studied in this paper.It was found that carbon(0.0140 wt%)and oxygen(0.0067 wt%)were the primary impurities for CVD and ED Re coatings,respectively.The diffusion of carbon into CVD Re coating caused higher microhardness near the substrate and helped to improve the bonding strength at the same time.The preferred orientation,microstructure and microhardness of ED Re coating were all susceptible to oxygen.The coating deposition uniformity of ED Re is obviously better than that of CVD Re coating,due to its intrinsic characteristics.The(002)-oriented,coarse columnar CVD Re coating exhibited better thermal stability compared with that of the<110>-oriented,fiber-like columnar ED Re coating,while the ED Re grains grew remarkably and the microstructure evolved toward the similar structure of CVD Re after annealing treatment.The diversity of Re coatings in microstructure could be attributed to the mobility of grain boundaries(affected by temperature and impurity)during deposition processes. 展开更多
关键词 Rhenium coating Graphite wafer Chemical vapor deposition Electrodeposition Molten salt Grain boundary mobility
Design of a hexagonal air-coupled capacitive micromachined ultrasonic transducer for air parametric array 认领
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作者 Xiaoli Zhang Hui Zhang Dachao Li 《纳米技术与精密工程(英文)》 CAS 2021年第1期26-35,共10页
An air parametric array can generate a highly directional beam of audible sound in air,which has a wide range of applications in targeted audio delivery.Capacitive micromachined ultrasonic transducer(CMUTs)have great ... An air parametric array can generate a highly directional beam of audible sound in air,which has a wide range of applications in targeted audio delivery.Capacitive micromachined ultrasonic transducer(CMUTs)have great potential for air-coupled applications,mainly because of their low acoustic impedance.In this study,an air-coupled CMUT array is designed as an air parametric array.A hexagonal array is proposed to improve the directivity of the sound generated.A finite element model of the CMUT is established in COMSOL software to facilitate the choice of appropriate structural parameters of the CMUT cell.The CMUT array is then fabricated by a wafer bonding process with high consistency.The performances of the CMUT are tested to verify the accuracy of the finite element analysis.By optimizing the component parameters of the bias-T circuit used for driving the CMUT,DC and AC voltages can be effectively applied to the top and bottom electrodes of the CMUT to provide efficient ultrasound transmission.Finally,the prepared hexagonal array is successfully used to conduct preliminary experiments on its application as an air parametric array. 展开更多
关键词 Capacitive micromachined ultrasonic transducer Air–coupled Wafer bonding process Bias-T circuit optimization Parametric array
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Study into grinding force in back grinding of wafer with outer rim 认领
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作者 Xiang-Long Zhu Yu Li +2 位作者 Zhi-Gang Dong Ren-Ke Kang Shang Gao 《先进制造进展:英文版》 SCIE CAS CSCD 2020年第3期361-368,共8页
Back grinding of wafer with outer rim(BGWOR)is a new method for carrier-less thinning of silicon wafers.At present,the effects of process parameters on the grinding force remain debatable.Therefore,a BGWOR normal grin... Back grinding of wafer with outer rim(BGWOR)is a new method for carrier-less thinning of silicon wafers.At present,the effects of process parameters on the grinding force remain debatable.Therefore,a BGWOR normal grinding force model based on grain depth-of-cut was established,and the relationship between grinding parameters(wheel infeed rate,wheel rotational speed,and chuck rotational speed)and normal grinding force was discussed.Further,a series of experiments were performed to verify the BGWOR normal grinding force model.This study proves that the BGWOR normal grinding force is related to the rotational direction of the wheel and chuck,and the effect of grinding mark density on the BGWOR normal grinding force cannot be ignored.Moreover,this study provides methods for reducing the grinding force and optimizing the back thinning process of the silicon wafer. 展开更多
关键词 Silicon wafer Back grinding of wafer with outer rim(BGWOR) Grinding force Grinding mark density
Scheduling Dual-Arm Cluster Tools With Multiple Wafer Types and Residency Time Constraints 认领
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作者 Jipeng Wang Hesuan Hu +2 位作者 Chunrong Pan Yuan Zhou Liang Li 《自动化学报:英文版》 SCIE EI CSCD 2020年第3期776-789,共14页
Accompanying the unceasing progress of integrated circuit manufacturing technology, the mainstream production mode of current semiconductor wafer fabrication is featured with multi-variety, small batch, and individual... Accompanying the unceasing progress of integrated circuit manufacturing technology, the mainstream production mode of current semiconductor wafer fabrication is featured with multi-variety, small batch, and individual customization, which poses a huge challenge to the scheduling of cluster tools with single-wafer-type fabrication. Concurrent processing multiple wafer types in cluster tools, as a novel production pattern, has drawn increasing attention from industry to academia, whereas the corresponding research remains insufficient. This paper investigates the scheduling problems of dual-arm cluster tools with multiple wafer types and residency time constraints. To pursue an easy-to-implement cyclic operation under diverse flow patterns,we develop a novel robot activity strategy called multiplex swap sequence. In the light of the virtual module technology, the workloads that stem from bottleneck process steps and asymmetrical process configuration are balanced satisfactorily. Moreover, several sufficient and necessary conditions with closed-form expressions are obtained for checking the system's schedulability. Finally, efficient algorithms with polynomial complexity are developed to find the periodic scheduling, and its practicability and availability are demonstrated by the offered illustrative examples. 展开更多
关键词 Cluster tools MULTIPLE WAFER TYPES SCHEDULING SEMICONDUCTOR manufacturing WAFER fabrication
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The Effect of Quartz Window on Bistability of the Silicon Wafer in Lamp-Based Reactor 认领
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作者 Valeriya P. Prigara Aleksandr N. Kupriyanov Vladimir V. Ovcharov 《材料科学与化学工程(英文)》 2020年第1期54-65,共12页
The effect of a quartz plate (window) on the silicon wafer temperature is studied in the conditions of the combined thermal transfer in a lamp-based chamber for the rapid thermal treatment (RTP) set up. The chamber fo... The effect of a quartz plate (window) on the silicon wafer temperature is studied in the conditions of the combined thermal transfer in a lamp-based chamber for the rapid thermal treatment (RTP) set up. The chamber for RTP is simulated by a radiative-closed thermal system including the influence of quartz window as a spectral filter of lamp emission and a source of emitted thermal radiation. Energy equations for thermal fluxes involved in the heat input and output from the working wafer and quartz window are solved in spectral approximation. The transfer characteristics that are defined by the temperature dependencies of the silicon wafer and the quartz window on the temperature of the heater are accounted. It is shown that temperature bistability in the silicon wafer initiates an induced bistability into the quartz window that does not reveal bistable behavior because of the linear temperature dependence of its total optical characteristics. A possibility for simulation of the quartz window by spectral restriction of the heater radiation is confirmed. The availability of the weak bistable effect in the mode of zero effective heat exchange coefficient of a non-radiative component of the thermal flux removed from the working wafer has been obtained. 展开更多
关键词 Lamp-Based Rector Silicon Wafer QUARTZ WINDOW Temperature and Optical BISTABILITY Induced BISTABILITY Effect
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Stability Behaviour of Monolayer Tetraether Lipids on the Amino-Silanised Silicon Wafer: Comparative Study between Langmuir-Blodgett Monolayers with Self-Assembled Monolayers 认领
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作者 Sri Vidawati Udo Bakowsky Urich Rothe 《材料物理与化学进展(英文)》 2020年第11期270-281,共12页
This study investigated the stability behaviour of molecular monolayer symmetric chemically modified tetraether lipids caldarchaeol-PO<sub>4</sub> on the amino-silanised silicon wafer using Langmuir-Blodge... This study investigated the stability behaviour of molecular monolayer symmetric chemically modified tetraether lipids caldarchaeol-PO<sub>4</sub> on the amino-silanised silicon wafer using Langmuir-Blodgett films, Self Assembling Monolayers (SAMs), ellipsometry, and atomic force microscopy (AFM). The monolayers of caldarchaeol-PO<sub>4 </sub>were stable on the solid surface amino-silanised silicon wafer. The organizations of molecular monolayers caldarchaeol-PO<sub>4</sub> by Langmuir-Blodgett method and SAMs have been analyzed. The surface of pressure in Langmuir-Blodgett processing is carried out monolayers caldarchaeol-PO<sub>4</sub> more flat island inhomogeneous. Another method of monolayers caldarchaeol-PO<sub>4</sub> by SAMs is showed a large flat domain. Monolayers caldarchaeol-PO<sub>4</sub> by Langmuir-Blodgett method seems to be stable and chemically resistant after washing with organic solvent and an additional treatment ultrasonification with various thickness lipids arround 2 nm to 6 nm. Conversely, monolayer caldarchaeol-PO<sub>4</sub> by SAMs appears fewer than monolayers caldarchaeol-PO<sub>4</sub> by Langmuir-Blodgett method, the thickness of various from 1 nm to 3 nm. 展开更多
关键词 Caldarchaeol-PO4 Langmuir-Blodgett Films Self Assembling Monolayers (SAMs) Amino-Silanised Silicon Wafer
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包装内初始氧对米威化饼干货架期的影响 认领
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作者 钱奕含 卢立新 +1 位作者 潘嘹 卢莉璟 《食品与发酵工业》 CAS CSCD 北大核心 2020年第8期136-141,共6页
为了探讨包装内氧气浓度对一种易氧化的新型食品--米威化饼干的货架期影响,该研究设计了4种不同包装内氧气浓度条件,并在50℃下对此产品进行了加速试验,测试了产品的过氧化值(peroxide value,POV)、色差及感官变化。除此之外,通过测试... 为了探讨包装内氧气浓度对一种易氧化的新型食品--米威化饼干的货架期影响,该研究设计了4种不同包装内氧气浓度条件,并在50℃下对此产品进行了加速试验,测试了产品的过氧化值(peroxide value,POV)、色差及感官变化。除此之外,通过测试不同储存温度条件下米威化的POV变化,建立了常氧下米威化货架期预测模型。试验结果表明,产品的POV随着时间延长而升高,且包装内氧气浓度越低,POV变化速率越低。50℃下,常氧包装的产品在第37天超过国标规定POV(0.25 g/100g),而真空包装的产品42 d的POV仅为0.088 g/100g,根据国标规定值预测货架期为83 d,氧气浓度对产品货架期影响显著。色差整体呈波动上升,感官品质随时间延长而下降。该产品常温常氧下预测货架期为107 d。该研究建立了在大气组分条件下米威化饼干的货架期预测模型,预测误差在±10%之内,为此产品的抗氧化包装设计提供了理论依据。 展开更多
关键词 米制品 威化饼干 货架期 氧化 初始氧
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高密度等离子体钝化层中电弧放电问题的改善 认领
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作者 田守卫 孙洪福 胡海天 《集成电路应用》 2020年第6期19-21,共3页
分析表明,晶圆的电弧放电现象在高密度等离子体钝化层制程中时常发生,随着半导体关键尺寸的减小,电弧放电的概率明显增加,尤其表现在0.13μm及以下晶圆制造过程中。而晶圆一旦发生电弧放电,会严重影响晶圆的良率及可靠性,所以控制及降... 分析表明,晶圆的电弧放电现象在高密度等离子体钝化层制程中时常发生,随着半导体关键尺寸的减小,电弧放电的概率明显增加,尤其表现在0.13μm及以下晶圆制造过程中。而晶圆一旦发生电弧放电,会严重影响晶圆的良率及可靠性,所以控制及降低电弧放电的概率可以减少产品的报废。根据电弧放电发生的机理,分析了在高密度等离子体钝化层制程中容易导致电弧放电的因素,从而通过增加衬底层SiO2的厚度,调整沉积钝化层的溅射率,优化整个沉积过程中的沉积溅射比率,可有效降低晶圆电弧放电发生的概率,对0.13μm及以下晶圆的改善尤为显著。 展开更多
关键词 集成电路制造 晶圆 高密度等离子体 电弧放电 钝化层 溅射率
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Sensitivity analysis of the surface integrity of monocrystalline silicon to grinding speed with same grain depth-of-cut 认领
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作者 Ping Zhou Zi-Guang Wang +3 位作者 Ying Yan Ning Huang Ren-Ke Kang Dong-Ming Guo 《先进制造进展:英文版》 SCIE CAS CSCD 2020年第1期97-106,共10页
Mechanisms for removal of materials during the grinding process of monocrystalline silicon have been extensively studied in the past several decades.However,debates over whether the cutting speed significantly affects... Mechanisms for removal of materials during the grinding process of monocrystalline silicon have been extensively studied in the past several decades.However,debates over whether the cutting speed significantly affects the surface integrity are ongoing.To address this debate,this study comprehensively investigates the effects of cutting speed on surface roughness,subsurface damage,residual stress,and grinding force for a constant grain depth-of-cut.The results illustrate that the changes in the surface roughness and subsurface damage relative to the grinding speed are less obvious when the material is removed in ductile-mode as opposed to in the brittle-ductile mixed mode.A notable finding is that there is no positive correlation between grinding force and surface integrity.The results of this study could be useful for further investigations on fundamental and technical analysis of the precision grinding of brittle materials. 展开更多
关键词 Rotational grinding Silicon wafer Surface integrity Cutting speed Residual stress
基于混合特征选择和超参优化的晶圆蚀刻缺陷预测方法 认领
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作者 陈晋贤 季颖娣 +1 位作者 林义征 朱定海 《计算机集成制造系统》 EI CSCD 北大核心 2020年第9期2396-2403,共8页
为了提高半导体晶圆制程中缺陷预测的准确率,提出一种混合特征选择和基于序列模型优化(SMBO)相结合的缺陷预测方法。该方法以对高维度、多噪声、多模态与线性不可分的数据具有良好适用性的随机森林和支持向量机两种机器学习算法为基础,... 为了提高半导体晶圆制程中缺陷预测的准确率,提出一种混合特征选择和基于序列模型优化(SMBO)相结合的缺陷预测方法。该方法以对高维度、多噪声、多模态与线性不可分的数据具有良好适用性的随机森林和支持向量机两种机器学习算法为基础,首先利用基于随机森林算法的稳定性筛选为特征评分,再基于序列前向搜索方法搜索降序排序的特征,依次创建支持向量机分类模型,并采用SMBO方法进行优化,最终选择表现最好且特征数量最少的模型进行缺陷预测。为了验证所提方法的有效性和优异性,使用蚀刻制程中的残渣缺陷和凹坑缺陷的实际工程数据进行预测对比分析,最终验证了其对晶圆制造过程中的缺陷具有优异的识别能力。 展开更多
关键词 混合特征选择 超参优化 随机森林 支持向量机 序列模型优化 晶圆 蚀刻缺陷预测
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晶圆表面光刻胶的涂覆与刮边工艺的研究 认领
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作者 金敏 王芳 《机械管理开发》 2020年第11期55-56,共2页
主要介绍了针对晶圆表层光刻胶的涂覆与刮边工艺,以及在研发过程中对生产工艺的总结.实践表明,该设备的研发成功满足了客户实现自动化生产的需求,有效提高了现场的生产效率,大大减少了人工成本,得到客户现场的一致好评.
关键词 晶圆 光刻胶 自动控制 匀胶工艺
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用于硅片切割废液Si和SiC分离旋流器的锥角影响研究 认领
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作者 华炜杰 袁惠新 +1 位作者 付双成 蒋敏杰 《太阳能学报》 EI CAS CSCD 北大核心 2020年第10期127-135,共9页
根据太阳能硅片切割废砂浆中Si(0.3~5.0μm)和SiC(5~25μm)颗粒细、易团聚以及密度均大于水等特性,利用重介质微型旋流器内强大的超重力场和剪切分散作用来分离Si和SiC。通过CFD软件Fluent 6.3.26数值模拟,探究锥角对重介质微型旋流器... 根据太阳能硅片切割废砂浆中Si(0.3~5.0μm)和SiC(5~25μm)颗粒细、易团聚以及密度均大于水等特性,利用重介质微型旋流器内强大的超重力场和剪切分散作用来分离Si和SiC。通过CFD软件Fluent 6.3.26数值模拟,探究锥角对重介质微型旋流器的流场及分离性能的影响,并用试验验证模拟的可靠性。结果表明,旋流器柱段长度一定时,同一截面高度随着锥角的增大,静压力和准自由涡切向速度增大,内旋流轴向速度减小,径向速度增大,湍流强度显著增强,压力降增大,而且锥角为8°时,牛顿分离效率达到最大值86.4%。旋流器长径比一定时,同一截面高度随着锥角的增大,静压力、切向速度和轴向速度均减小,径向速度增大,湍流强度略微增强,压力降缓慢减小,牛顿分离效率随着锥角的增大而减小,锥角8°时的分离效果较好。根据压力降和牛顿效率,定长径比变锥角与定柱段长度变锥角相比可得到更好的性能。 展开更多
关键词 硅片 分离 回收 计算流体力学 微型旋流器 锥角
浅论汽车发电机用DBR技术调节器制造过程失效模式和控制计划 认领
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作者 胡云峰 《汽车电器》 2020年第6期36-39,共4页
随着用户对汽车智能化、网联化要求的不断提高,汽车电器的功能也需要不断增多,电压调节器作为汽车发电机的核心部件也需要由传统的调节电压单一功能转变为满足不同要求的多功能,而随着功能的增多,调节器的失效模式也在不断增加。要控制... 随着用户对汽车智能化、网联化要求的不断提高,汽车电器的功能也需要不断增多,电压调节器作为汽车发电机的核心部件也需要由传统的调节电压单一功能转变为满足不同要求的多功能,而随着功能的增多,调节器的失效模式也在不断增加。要控制多功能调节器失效模式的产生,重要在制造过程进行控制,本文对汽车发电机用DBR技术调节器的制造过程失效模式进行总结和分析,并针对具体失效模式制定了专业的控制计划。 展开更多
关键词 汽车发电机用DBR技术调节器 制造过程失效模式 控制计划 MCB铝基板 键合 晶片 烧录
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基于十六项误差模型算法的GCPW校准标准研制 认领
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作者 周瑞 王一帮 +1 位作者 刘晨 栾鹏 《宇航计测技术》 CSCD 2020年第4期35-40,共6页
开发了用于表征W波段电路的在片十六项误差模型GCPW校准标准。GCPW校准标准与被测晶体管制作在薄的砷化镓(GaAs)衬底上,可有效消除校准标准和被测件由于衬底、边界条件不一致带来的系统误差。校准标准设计中采用合适的尺寸和过孔工艺来... 开发了用于表征W波段电路的在片十六项误差模型GCPW校准标准。GCPW校准标准与被测晶体管制作在薄的砷化镓(GaAs)衬底上,可有效消除校准标准和被测件由于衬底、边界条件不一致带来的系统误差。校准标准设计中采用合适的尺寸和过孔工艺来保证单模传输(减小平行板模式和表面波模式)。为了精确标定十六项误差模型校准标准的散射参数,同一片晶圆片还设计了多线TRL辅助校准标准。十六项误差模型校准标准和商用的阻抗标准(LRRM)测试同一无源器件,测试结果表明前者在测试串扰方面更为准确。实验结果表明,GCPW校准标准可替代传统的多线TRL校准标准,用于W波段及以上的在片测试。 展开更多
关键词 在片 十六项误差模型 校准标准 散射参数
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110 GHz可溯源的On-wafer GaAs基Multi-TRL校准标准件研制 认领 被引量:2
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作者 袁思昊 刘欣萌 黄辉 《计量学报》 CSCD 北大核心 2019年第5期760-764,共5页
设计制作了用于1~110GHzOn-wafer散射参数测试系统自校准的GaAs基Multi-TRL校准标准件。主要验证了Multi-TRL校准标准件设计的正确性;经过与国外计量标准及商用校准件比对,还验证了在频率范围1GHz~110GHz,用于Multi-TRL校准的校准标准... 设计制作了用于1~110GHzOn-wafer散射参数测试系统自校准的GaAs基Multi-TRL校准标准件。主要验证了Multi-TRL校准标准件设计的正确性;经过与国外计量标准及商用校准件比对,还验证了在频率范围1GHz~110GHz,用于Multi-TRL校准的校准标准件的准确性。 展开更多
关键词 计量学 共面波导 W波段 On-wafer 砷化镓 Multi-TRL校准件 散射参数
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Heterogeneous Ⅲ-Ⅴ silicon photonic integration:components and characterization 认领
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作者 Shang-jian ZHANG Yong LIU +2 位作者 Rong-guo LU Bao SUN Lian-shan YAN 《信息与电子工程前沿:英文版》 SCIE EI CSCD 2019年第4期472-480,共9页
Heterogeneous Ⅲ-Ⅴ silicon(Si) photonic integration is considered one of the key methods for realizing power-and cost-effective optical interconnections, which are highly desired for future high-performance computers... Heterogeneous Ⅲ-Ⅴ silicon(Si) photonic integration is considered one of the key methods for realizing power-and cost-effective optical interconnections, which are highly desired for future high-performance computers and datacenters. We review the recent progress in heterogeneous Ⅲ-Ⅴ/Si photonic integration, including transceiving devices and components. We also describe the progress in the on-wafer characterization of photonic integration circuits, especially on the heterogeneous Ⅲ-Ⅴ/Si platform. 展开更多
关键词 HETEROGENEOUS PHOTONIC INTEGRATION Optical INTERCONNECTION On-wafer CHARACTERIZATION
钽酸锂黑片的制备与性能研究 认领
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作者 龙勇 于明晓 +5 位作者 李和新 石自彬 王璐 丁雨憧 徐扬 吴兆刚 《压电与声光》 CAS 北大核心 2019年第3期340-343,共4页
为了获得高均匀性、低热释电的钽酸锂(LT)晶片,采用粉末掩埋法对42°Y-LT晶片进行了还原处理。结果表明,还原处理后的晶片电阻率为3.98×10^10Ω·cm;在365nm处透过率约为36.5%,透过率均匀性为1.15;热导率为2.66W/(m·... 为了获得高均匀性、低热释电的钽酸锂(LT)晶片,采用粉末掩埋法对42°Y-LT晶片进行了还原处理。结果表明,还原处理后的晶片电阻率为3.98×10^10Ω·cm;在365nm处透过率约为36.5%,透过率均匀性为1.15;热导率为2.66W/(m·K),热膨胀系数为2.79×10^-6K^-1,满足器件使用要求。通过声表面波器件验证实验表明,晶片抗静电能力效果明显,器件成品率较高,一致性好。 展开更多
关键词 钽酸锂 还原处理 电阻率 均匀性 晶片
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集成电路现状与发展趋势 认领
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作者 吕菲 《电子工业专用设备》 2019年第4期37-41,共5页
通过中外集成电路产业的对比和中国集成电路未来发展趋势的分析,准确阐述了中国集成电路产业的现状。近年来,中国集成电路产业一直处于快速发展的模式,市场规模和技术水平都在不断提高,集成电路的设计、制造、封测产业格局越来越均衡。... 通过中外集成电路产业的对比和中国集成电路未来发展趋势的分析,准确阐述了中国集成电路产业的现状。近年来,中国集成电路产业一直处于快速发展的模式,市场规模和技术水平都在不断提高,集成电路的设计、制造、封测产业格局越来越均衡。全球半导体制造正在向中国转移,这种转变有助于提高中国半导体制造的技术水平,缩短与先进制程的差距。政策和资金的支持,增加了企业的投资信心,创造了良好的产业环境。 展开更多
关键词 晶圆 集成电路设计 集成电路制造 集成电路封测 复合增长率
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Scalable and ultrafast epitaxial growth of single-crystal graphene wafers for electrically tunable liquid-crystal microlens arrays 认领 被引量:2
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作者 Bing Deng Zhaowei Xin +18 位作者 Ruiwen Xue Shishu Zhang Xiaozhi Xu Jing Gao Jilin Tang Yue Qi Yani Wang Yan Zhao Luzhao Sun Huihui Wang Kaihui Liu Mark H. Rummeli Lu-Tao Weng Zhengtang Luo Lianming Tong Xinyu Zhang Changsheng Xie Zhongfan Liu Hailin Peng 《科学通报:英文版》 SCIE EI CSCD 2019年第10期659-668,共10页
The scalable growth of wafer-sized single-crystal graphene in an energy-efficient manner and compatible with wafer process is critical for the killer applications of graphene in high-performance electronics and optoel... The scalable growth of wafer-sized single-crystal graphene in an energy-efficient manner and compatible with wafer process is critical for the killer applications of graphene in high-performance electronics and optoelectronics. Here, ultrafast epitaxial growth of single-crystal graphene wafers is realized on singlecrystal Cu90Ni10(1 1 1) thin films fabricated by a tailored two-step magnetron sputtering and recrystallization process. The minor nickel(Ni) content greatly enhances the catalytic activity of Cu, rendering the growth of a 4 in. single-crystal monolayer graphene wafer in 10 min on Cu90Ni10(1 1 1), 50 folds faster than graphene growth on Cu(1 1 1). Through the carbon isotope labeling experiments, graphene growth on Cu90Ni10(1 1 1) is proved to be exclusively surface-reaction dominated, which is ascribed to the Cu surface enrichment in the Cu Ni alloy, as indicated by element in-depth profile. One of the best benefits of our protocol is the compatibility with wafer process and excellent scalability. A pilot-scale chemical vapor deposition(CVD) system is designed and built for the mass production of single-crystal graphene wafers, with productivity of 25 pieces in one process cycle. Furthermore, we demonstrate the application of single-crystal graphene in electrically controlled liquid-crystal microlens arrays(LCMLA), which exhibit highly tunable focal lengths near 2 mm under small driving voltages. By integration of the graphene based LCMLA and a CMOS sensor, a prototype camera is proposed that is available for simultaneous light-field and light intensity imaging. The single-crystal graphene wafers could hold great promising for highperformance electronics and optoelectronics that are compatible with wafer process. 展开更多
关键词 GRAPHENE ULTRAFAST growth CuNi(1 1 1)thin film Single CRYSTAL wafer Liquid CRYSTAL MICROLENS arrays
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